This invention relates to a computer system including an accelerator utilizing an FPGA.
In recent years, a technology that utilizes a field-programmable gate array (FPGA) has been employed to make it perform part of data processing. For example, U.S. Pat. No. 8,095,508 B discloses data processing with a device including an FPGA coupled to a computer.
When an FPGA is used, collision of neutrons may generate a soft error that causes an erroneous result of hardware implementation.
As described in “Error Detection and Recovery Using CRC in Altera FPGA Devices” (ALTERA, Application Note 357), the vendors of FPGAs provide functions for soft error detection and recovery. A soft error checking function employed by an FPGA vendor divides the FPGA into small regions called frames and calculates cyclic redundancy codes (CRC) for the frames in advance. The checking function of the FPGA determines whether any error exists in each frame with the CRC and if an error exists, transmits an error signal to the external of the FPGA. US 2014/0095928 A discloses a storage control device in which, when a detection unit detects a soft error, a communication controller changes the state of the communication path between the communication device and the host device into a busy state.